Projects, Digital design, C programming
Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
Write RTL code for mod9 counter?
Basic SV and UVM Questions
Throughput vs latency in computer architecture.
1. What is setup, hold time. Reason of metastability. 2. How to reduce setup time, hold time. 3. A C code to check if a given number is divisible by 2 4. Difference between mealy and moore machine 5. Project and resume based questions
Questions based on CV mostly questions are from SV, UVM, Protocols
tell me the UVM testbench execution flow
How would you write a testplan for a FIFO? Create an AND gate from NAND gates. How do you select 2 values from an array whose sum is some value p in linear time?
1 easy and 1 medium level leet code problem along with unit test and expected output of a program.
Describe the testbench hierarchy in UVM
Viewing 961 - 970 interview questions
See Interview Questions for Similar Jobs
Design Verification EngineerSenior Physical Design EngineerSenior Vlsi Design EngineerSenior Asic Physical Design EngineerSenior Asic Fpga Design EngineerSenior Dft EngineerSenior Asic Verification EngineerFpga Development EngineerVlsi Design EngineerSenior Asic Design EngineerPhysical Design EngineerStaff Physical Design EngineerSystems Design EngineerDesign VerificationSenior Hardware Design EngineerHardware Design EngineerAsic Physical Design EngineerVerification Manager