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Senior Fpga Design Engineer Interview Questions

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151 senior fpga design engineer interview questions shared by candidates

1. 30 mins phone screening about my resume and my background. 2. a) fill out a truth table for 4 to 1 mux. b) implement an 8 to 1 mux with 3 given 4 to 1 mux. c) 1)Given few declared variables in a struct C/C++, calculates the total number of bits that allocate and occupy in the memory. EX. ..... char hello; uint_32 hi[5];....... ANS: total bits of memory require = 8 + 32 * 5 = 168 bits. 2) Imagine that an HDL code is sending 168 bits of data to the two variables in struct C/C++. Fill out the bit length of each variable. ANS: hello[7:0] and hi[167:8]. Very easy questions.
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FPGA Design and Verification Engineer I

Interviewed at HPR

4.2★
Aug 7, 2021

1. 30 mins phone screening about my resume and my background. 2. a) fill out a truth table for 4 to 1 mux. b) implement an 8 to 1 mux with 3 given 4 to 1 mux. c) 1)Given few declared variables in a struct C/C++, calculates the total number of bits that allocate and occupy in the memory. EX. ..... char hello; uint_32 hi[5];....... ANS: total bits of memory require = 8 + 32 * 5 = 168 bits. 2) Imagine that an HDL code is sending 168 bits of data to the two variables in struct C/C++. Fill out the bit length of each variable. ANS: hello[7:0] and hi[167:8]. Very easy questions.

• Tell me about yourself • Rate yourself in Verilog, SV, UVM • Verilog code in generating clock pulse high in first 3 clock pulses and low in rest of clock pulses and again clock pulse should be high on 10th to 13th. This cycle should repeat. (10 min) • FSM 1011 overlap and explain that • Mealy and moore machine. • Project (communication protocol, fpga projects, ASIC project) • Setup and hold time • What is metastability • How to minimize the violation • Most priority violation setup or hold • General question • If you giving the opportunity in fpga or dsp you will ready to work • Tell me about NOKIA
avatar

FPGA Design Engineer

Interviewed at Nokia

4★
Sep 19, 2023

• Tell me about yourself • Rate yourself in Verilog, SV, UVM • Verilog code in generating clock pulse high in first 3 clock pulses and low in rest of clock pulses and again clock pulse should be high on 10th to 13th. This cycle should repeat. (10 min) • FSM 1011 overlap and explain that • Mealy and moore machine. • Project (communication protocol, fpga projects, ASIC project) • Setup and hold time • What is metastability • How to minimize the violation • Most priority violation setup or hold • General question • If you giving the opportunity in fpga or dsp you will ready to work • Tell me about NOKIA

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