They asked to explained me something from my resume that matches the skills of the job description.
Senior Fpga Design Engineer Interview Questions
151 senior fpga design engineer interview questions shared by candidates
C++ and verilog, fpga questions
Delay the bus signal with BRAM.
Easy questions like write DFF etc.
You have a device connected with a I2C bus. You send the data to the FIFO inside this device. How can you let the master know about FIFO overflow?
Reverse an array in-place
Can't remember.
Bus protocols like SPI, ARM etc
Previous experience and coding part
Questions related to CDC and Verilog/VHDL. one behavioral question. Questions from the resume.
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