Questions about cache coherency, C++, fork-join, Verilog
Verification Engineer Interview Questions
3,655 verification engineer interview questions shared by candidates
array to be filled with unique incremental value using constraints of systemverilog
Favorite project details
Tell me about yourself
How would you handle an irate customer? What process would you follow to resolve the issue?
All kinds of fork joins
Test cases for a 2 input, 2bit adder.
Difference between Nonblocking vs blocking assignments
Explain about FIFO, Clk generation, State machine
Verilog based questions - circuit was given and then i had to give an optimized code for it.
Viewing 2391 - 2400 interview questions