Questions on interface, clocking blocks, assertions, uvm, X propagation.
Verification Engineer Interview Questions
3,655 verification engineer interview questions shared by candidates
SystemVerilog assertion and functional coverage coding.
Dont remember much but mostly code deep dives and situational questions related to work.
Describe tokenizing concepts?
Didn't attend the interview
how to get fibonacci sequence
Describe what a virtual function does?
I was asked to write system verilog constraints for a variety of random stimulus needs.
Register renaming
What is VIPT cache?
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