System Verilog and Formal Verification
Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
Example verification cases for a two-port memory block with address, data in, data out and a r/w enable.
asked about uvm and system verilog.few questions about sv constraints
Explain the I2C protocol
Describe the testbench you created for a particular project
Q: What is the use of the factory in UVM?
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Draw the IDD diagram (current as a function of time) of an inverter when the input switches from OFF to ON.
related to projects and your role in the project
Difference between AXI and AHB and based on AXi channels
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