They asked me to sort an array with an specific condition, without sorting
Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
Define verilog ,systemverilog. Memory /cache
Write a function that creates a randomized array of integers from 1 to 100, each number appearing once.
SV, UVM and Digital Electronics Questions.
1.timeout function 2.AXi assertions 3.display through command line arguments
1. Draw the CMOS circuit for NAND gate and explain it's working. 2. Difference between Low pass filter and High pass filter. 3. Frequency response of unit step function. 4. What is sampling and aliasing? 5. Rigorous analysis of testbench code for a given DUT.
what is setup and hold time?
Pretty basic digital design questions- timing, logic design etc.. Signal processing questions-sampling, nyquist rate definition, quantization error etc..
Phone Interview with a Design Verification Engineer: Questions on Digital Signal Processing, Analog basics and System Verilog basics.
Asked some questions on C++, constraints, and basic UVM
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