Explain the structure of uvm verification environment.
Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
Where do you see yourself in 5 years?
Few puzzles and Projects in my resume
Teamwork that related to the position.
Questions related to pipelining, hazards, in-order processor, out of order processor, Register renaming, branch prediction, caches and virtual memory
Decode a CMOS transistor diagram (complex)
FIFO, LIFO in Verilog
Some basic questions/tasks about C programming (pointers, arrays..), design task for receiving data bytes from the transmitter (C programming), Asked to explain different parts of some old SOC configuration. For people studying only Electronics I would suggest going through Software Engineering lectures from other courses to know about how memory is managed in a SOC and CPU. Ideally read about the Architecture of CPU and Microcontrollers as I was asked this in all 3 Interviews with ARM. I only studied Electronics and had no courses related to this except when we briefly looked into simple microcontrollers without going into detail so it was good decision going through Software Engineering course notes before the interview.
That's all i can share . Practice your basics. All the best !
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